Integrated circuits, or ICs, are created by patterning a substrate and materials deposited on the substrate. The substrate is typically a semiconductor wafer. The patterned features make up devices and interconnections. This process generally starts with a designer creating an integrated circuit by hierarchically defining functional components of the circuit using a hardware description language. From this high-level functional description, a physical circuit implementation dataset is created, which is usually in the form of a netlist. This netlist identifies logic cell instances from a cell library, and describes cell-to-cell connectivity.
Many phases of these electronic design activities may be performed with computer aided design (CAD) tools or electronic design automation (EDA) systems. For example, an integrated circuit designer may use a set of layout EDA application programs, such as behavior and logic synthesis tools, a floor planning tool, a placement tool, a router, a layout editor, or a post-route optimizer to create, modify, and/or optimize integrated circuit designs.
The task of all routers is the same—routers are given some pre-existing polygons consisting of pins, terminals, or pads on cells and optionally some pre-routes from the placers to create global routes, conduit routes, or detail routes so that all pins assigned to different nets are connected by wires and vias, that all wires and vias assigned to different nets do not overlap, and that all design rules are obeyed. That is, a router fails when two pins on the same net that should be connected are open, when two pins on two different nets that should remain open are shorted, or when some design rules are violated during routing. A router is thus expected to connect two points with a single wire for all but some special nets such as the power net, the ground net, the clock net, nets for busses, spine routes connecting multiple pins to the trunk of a spine, or multi-strand nets for carrying high or higher current.
Conventional routers (global router, conduit router, channel router, and detail router) identify various pins, pads, and terminals that must be interconnected and introduce various Steiner points to solve a rectilinear minimum spanning tree problem in order to find the respective global, conduit, channel, and detail routes. These approaches may attempt to add redundant connections or multiple connections with redundant vias, double-cut vias, bar vias, etc. by introducing additional Steiner points. Although these approach may achieve their intended purposes for conventional electronic designs, these approaches may nevertheless fail when processing modern electronic designs with 14-nm or smaller advanced nodes due to insufficient routing resources, especially in multiple-patterning terms, that have rendered larger vias far less favorable. Moreover, the introduction of additional Steiner points in implementing a route disturbs the original connectivity because a Steiner point breaks the original route on which the Steiner point lies. Some other conventional approaches rely on remastering techniques for reducing feature sizes on lithography. Recent research has found evidence showing that the remastering process may not even achieve its intended purposes in advanced nodes having 14-nm or smaller advanced nodes.
Therefore, there exists a need for a method, a system, and an article of manufacture for implementing additional connectivity for electronic designs.